1. Field of the Invention
The present invention relates to a potential generating circuit, and particularly to a potential generating circuit charging and discharging an output node in order that a potential of the output node becomes a potential corresponding to a reference potential.
2. Description of the Background Art
With the purpose to reduce power consumption, there has been heretofore provided an internal power supply potential generating circuit for generating an internal power supply potential VO lower than an external power supply potential VCC0 in a semiconductor integrated circuit device.
FIG. 21 is a circuit diagram showing a configuration of such an internal power supply potential generating circuit. In FIG. 21, the internal power supply potential generating circuit includes: an operational amplifier 151; P-channel MOS transistors 152 to 154; and N-channel MOS transistors 155 to 157. Operational amplifier 151 constitutes a voltage follower and outputs a current so as to cause a potential VDDS at a node N151 to coincide with a reference potential VR0. MOS transistors 152, 155, 153 and 156 are connected in series between node N151 and a line at ground potential GND. MOS transistors 157 and 154 are connected in series between a line at external power supply potential VCC0 and the line at ground potential GND. The gates of N-channel MOS transistors 155 and 157 are both connected to the drain of N-channel MOS transistor 155, and the gates of P-channel MOS transistors 153 and 154 are both connected to the drain of P-channel MOS transistor 153. The gates of MOS transistors 152 and 156 are both connected to an output node N157 between MOS transistors 157 and 154. A potential appearing at node N157 is internal power supply potential VO.
Transistor parameters of MOS transistors 152, 155, 153 and 156 are set in order that a potential VC at a node N155 between MOS transistors 155 and 153 is VDDS/2=VR0/2 when internal power supply potential VO is VDDS/2=VR0/2. Furthermore, not only is a threshold voltage of N-channel MOS transistor 157 set to a value higher than that of N-channel MOS transistor 155, but a threshold voltage of P-channel MOS transistor 154 is also set to a value higher than that of P-channel MOS transistor 153 in order that no through current flows into the line at ground potential GND from the line at external power supply potential VCC0 through MOS transistors 157 and 154. With such setting, MOS transistors 157 and 154 are both non-conductive when output potential VO resides in a dead band E1 between a lower limit value VL=VR0/2−ΔV1 and an upper limit value VH=VR0/2+ΔV2.
FIG. 22 is a graph showing an operation of the internal power supply potential generating circuit shown in FIG. 21. In FIG. 22, a straight line E in FIG. 22 shows a relationship between output potential VO and a drive current I of the internal power supply potential generating circuit. MOS transistors 157 and 154 becomes non-conductive to cause drive current I to be zero when output potential VO resides in dead band E1. With internal power supply potential VO higher than upper limit VH, not only a resistance value of P-channel MOS transistor 152 becomes higher, but a resistance value of N-channel MOS transistor 156 also becomes lower to lower gate potentials of MOS transistors 157 and 154, to cause P-channel MOS transistor 154 to be conductive, to thereby cause a discharge current to flow and to lower internal power supply potential VO. With internal power supply potential VO lower than lower limit value VL, not only a resistance value of P-channel MOS transistor 152 become lower, but a resistance value of N-channel MOS transistor 96 also becomes higher, to raise gate potentials of MOS transistors 157 and 154, to cause N-channel MOS transistor 157 to be conductive, to thereby cause a charge current flow and to raise internal power supply potential VO. Therefore, internal power supply potential VO is held at a potential between lower limit value VL and upper limit value VH.
In such an internal power supply potential generating circuit, a necessity arises for setting a source-to-drain voltage Vsdp of P-channel MOS transistor 152, a threshold voltage Vthn of N-channel MOS transistor 155, a threshold voltage Vthp of P-channel MOS transistor 153 and a drain-to-source voltage Vdsn of N-channel MOS transistor 156 in order that VC=VDDS/2=VR0/2 when VO=VC.
With lower VDDS, miniaturized layout, constraint from other circuits, fluctuations in fabrication parameters and others, more of difficulty has become a reality in fabrication of MOS transistors in matching Vsdp, Vthn, Vthp and Vdsn with design values. A result ends up with generation of an error voltage ΔV between internal power supply potential VO and a target potential VR0/2 as shown in FIG. 23 without matching Vsdp, Vthn, Vthp and Vdsn with design values.
In a conventional internal power supply potential generating circuit, not only were threshold voltages of N-channel MOS transistors 155 and 157 adjusted, but threshold voltages of P-channel MOS transistors 153 and 154 were also adjusted to thereby set a width of dead band E1, whereas control of a width of dead band E1 has become harder by a tendency toward lower VDDS and other reasons.